Conventional Quad Flat Non-leaded (QFN) semiconductor package is structured as disclosed in U.S. Pat. No. 6,583,499 and is shown in FIG. 4, wherein a chip 41 is attached to a die pad 420 of a lead frame 42 and is electrically connected to leads 421 of the lead frame 42 via gold wires 43, and an encapsulant 44 is formed for encapsulating the chip 41, the lead frame 42 and the gold wires 43, with bottom surfaces of both the die pad 420 and the leads 421 being exposed from the encapsulant 44, such that the leads 421 can be implanted with solder balls or electrically connected to a printed circuit board (PCB) by solder paste.
The above QFN package advantageously does not have the leads extended out of the encapsulant and thus does not occupy a relatively larger area of the PCB unlike a Quad Flat Package (QFP). In view of the size and thickness requirements for the current semiconductor package, the QFN package has a satisfactorily small size, but it is still not considered thin enough or cannot be further reduced in thickness with the thickness of the lead frame (usually up to 200 μm) being taken into account.
Accordingly, to solve the above problem in terms of thickness, a semiconductor package without a lead frame is provided as disclosed in U.S. Pat. No. 5,830,800. This semiconductor package 5, as shown in FIG. 5, includes a plurality of electroplated pads 51 formed on a copper carrier (not shown), wherein the thickness of the electroplated pads 51 is only about 6 μm. A chip 52 is mounted on the copper carrier by silver paste, and is electrically connected to the electroplated pads 51 via a plurality of gold wires 53. An encapsulant 54 is formed for encapsulating the electroplated pads 51, the chip 52 and the gold wires 53. After forming the encapsulant 54, the copper carrier is removed by a chemical etching process, such that bottom surfaces of the electroplated pads 51 are exposed from the encapsulant 54. Finally, a plurality of solder balls 55 are implanted to the exposed electroplated pads 51.
Although the above semiconductor package 5 is thinner than a conventional lead-frame-based semiconductor package, only the electroplated pads 51 under the chip 52 serve as a heat dissipating medium for the chip 52 and thus make the total heat dissipating area of the semiconductor package 5 limited. Consequently, heat generated from the chip 52 during operation cannot be dissipated effectively only through the electroplated pads 51, such that electrical performance of the semiconductor package 5 may be adversely affected and even the chip 52 may be damaged.
To address the problem of heat dissipation for the chip, it is preferable to incorporate the die pad used in the QFN package into the above semiconductor package 5 by a plating technique to have the chip connected to the electroplated die pad such that the heat from the chip can be dissipated directly to an external environment through the electroplated die pad having a relatively larger heat dissipating area. This forms a semiconductor package 6 as shown in FIG. 6. However, if the surface area of the electroplated die pad 61 is larger than or equal to that of the chip 62 and if there are signal pads (not shown) or passive components 630 provided in a region, corresponding to the electroplated die pad 61, of a circuited board 63 to which the semiconductor package 6 is mounted, when the electroplated die pad 61 is bonded to the corresponding region of the circuit board 63 by solder paste 64, the solder paste 64 would cover and/or come into contact with the signal pads or the passive components 630, thereby resulting in short circuit.
In order to avoid short circuit, a strategy is to position the signal pads or the passive components 630 outside the region of the circuit board 63 covered by the solder paste 64. However, this undesirably alters the circuit layout of the circuit board, and thus increases the costs, sets a limitation on the circuit layout, as well as increases the design difficulty.
As an alternative, a semiconductor package 7 without altering the circuit layout of the circuit board is provided as shown in FIG. 7, wherein the electroplated die pad 71 is reduced to a size smaller than that of the chip 75, such that the solder paste 74 for bonding the electroplated die pad 71 to the circuit board 73 would not cover or come into contact with the signal pads or passive components 730 that are formed on the circuit board 73 and under the chip 75. However, if the thickness of the electroplated die pad 71 is smaller than 10 μm, space S between a bottom surface of the chip 75 and a bottom surface of the encapsulant 76 may become relatively small, for example, there may be a small distance (between 20 μm and 30 μm) left from the bottom surface of the chip 75 to the bottom surface of the encapsulant 76. As a result, a resin compound for forming the encapsulant 76 cannot be filled into the space S completely during a molding process of forming the encapsulant 76, such that voids 760 and/or recesses 761 are possibly formed, thereby degrading the reliability of the semiconductor package due to the voids 760 and/or adversely affecting the appearance of the semiconductor package due to the recesses 761.
As another alternative, if it is to alter the circuit layout of the circuit board, a semiconductor package 8 is provided as shown in FIG. 8, wherein signal pads or passive components 830 of the circuit board 83 are relocated to positions outside the region under the electroplated die pad 81, making the solder paste 84 not cover or come into contact with the signal pads or the passive components 830. Moreover, a ground ring 850 and a power ring 851 are additionally provided and are electrically connected to the chip 85. However, during a reflowing process for bonding the semiconductor package 8 to the circuit board 83 via the solder paste 84, since the ground ring 850 is located very close to the power ring 851, the solder paste 84 being reflowed may come into contact with the power ring 851 and ground the power ring 851 to the circuit board 83, thereby causing short circuit as indicated by S1 in FIG. 8. Accordingly, even by altering the circuit layout of the circuit board 83, none of the foregoing semiconductor packages without chip carriers can be adapted to incorporate a power ring to improve the electrical performance thereof without having the aforementioned drawbacks.
Therefore, the problem to be solved here is to provide a semiconductor package without a chip carrier, which can effectively overcome or eliminate the foregoing drawbacks.